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January 1998
Features
S IG N DES EW t RN t er a D FO 0 C en s c DE 0 5 or t t MEN e HI3 up p o m/ COM Se hnical S ntersil.c E R .i ec N OT www ur T ct o SIL or R onta or c 8-INTE 1-88
(R)
HI2309
Triple 10-Bit, 50 MSPS, 3-Channel D/A Converter
Description
The HI2309 is a triple 10-bit, high-speed, CMOS D/A converter designed for video band use. It has three separate, 10-bit, pixel inputs, one each for red, green, and blue video data. A single 5.0V power supply and pixel clock input is all that is required to make the device operational. A bias voltage generator is internal. Each channel clock input can be controlled individually, or connected together as one. The HI2309 also has BLANK video control signal.
* Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 10-Bit * Maximum Conversion Speed . . . . . . . . . . . . . . . 50MHz * RGB 3-Channel Input/Output * Differential Linearity Error . . . . . . . . . . . . . . . 0.5 LSB * Low Power Consumption . . . . . . . . . . . . . . . . . . 200mW (200 Load for 2V P-P Output) * Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . +5V Single * Low Glitch * Direct Replacement for Sony CXD2309
Ordering Information
PART NUMBER HI2309JCQ TEMP. RANGE ( oC) -20 to 75 PACKAGE 48 Ld MQFP PKG. NO. Q48.12x12-S
Applications
* Digital TV * Graphics Display * High Resolution Color Graphics * Video Reconstruction * Instrumentation * Image Processing * I/Q Modulation
Pinout
HI2309 (MQFP) TOP VIEW
DVDD AVSS RO AVDD AVDD AVDD VG AVSS GO AVSS VREF BO
(LSB) R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 G0 (LSB) G1
1 2 3 4 5 6 7 8 9 10
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
IREF VB DVSS BCK GCK RCK B9 B8 B7 B6 B5 B4
26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24
G8 G9
G2
G3
G4 G5
G6
G7
B0 (LSB) B1
B2
B3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 10-1
File Number
4118.2
HI2309 Functional Block Diagram
43 AVSS 42 RO
(LSB) R0 R1 R2 R3 R4 R5 R6 R7 R8
1 2 3 4 5 6 7 8 9 DECODER DECODER LATCHES
4 LSBs CURRENT CELLS
6 LSBs CURRENT CELLS
CLOCK GENERATOR
R9 10 RCK 31 (LSB) G0 11 G1 12 G2 13 G3 14 G4 15 G5 16 G6 17 G7 18 G8 19 G9 20 GCK 32 (LSB) B0 21 B1 22 B2 23 B3 24 B4 25 B5 26 B6 27 B7 28 B8 29 B9 30 BCK 33 DVDD 48 BIAS VOLTAGE GENERATOR CURRENT CELLS (FOR FULL SCALE) DECODER CLOCK GENERATOR 38 VG DECODER LATCHES 6 LSBs CURRENT CELLS 4 LSBs CURRENT CELLS 47 AVSS 46 BO DECODER CLOCK GENERATOR DECODER LATCHES 6 LSBs CURRENT CELLS 4 LSBs CURRENT CELLS 45 AVSS 44 GO
41 AVDD 40 AVDD 39 AVDD
+
-
37 VREF 36 IREF
VB 35 DVSS 34
10-2
HI2309 Pin Descriptions
PIN NO. 1 to 10 11 to 20 21 to 30 SYMBOL R0 to R9 G0 to G9 B0 to B9
1 TO 30
EQUIVALENT CIRCUIT
DVDD
DESCRIPTION Digital Input.
DVSS
31 32 33
RCLK GCLK BCLK
31 TO 33
DVDD
Clock pin.
DVSS
34 35
DVSS VB
DVDD DVDD
Digital GND. Connect an approximately 0.1F capacitor.
35
+
-
DVSS
36 37 38
IREF VREF VG
36 AVDD
AVDD
AVDD
Connect a "16R" resistor which is 16 times the output resistance "R". Sets an output full scale value. Connect an approximately 0.1F capacitor.
AVDD
+
-
AVDD 37 38
AVSS
AVSS
39 to 41 42 44 46
AV DD RO GO BO
42 44 46 AVDD
Analog VDD . Current Output. Output can be obtained by connecting a resistor (200 typical).
AVSS
AVSS
43, 45, 47 47, 48
AV DD DVDD
Analog GND. Digital VDD .
10-3
HI2309
Absolute Maximum Ratings TA = 25oC
Supply Voltage (V DD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltage (V IN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . .0mA to 15mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC 150oC
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (oC/W)
Operating Conditions
Supply Voltage AVDD , AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V DV DD , DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V Reference Input Voltage (V REF) . . . . . . . . . . . . . . . . . .0.5V to 2.0V Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Min) Temperature Range (TOPR). . . . . . . . . . . . . . . . . . . . -20oC to 75oC
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Resolution Maximum Conversion Speed Linearity Error Differential Linearity Error Output Full Scale Voltage Output Full Scale Current Output Offset Voltage Supply Current Digital Input Current High Level Low Level Digital Input Voltage High Level Low Level
fCLK = 50MHz, VDD = 5V, R = 200 , VREF = 2.0V, TA = 25oC SYMBOL n fMAX EL ED V FS IFS VOS IDD IIH IIL V IH VIL VOC tS tH tPD GE CT SNR For ROUT = 100, 1VP-P Output For 10MHz Sine Wave Output For 1MHz Sine Wave Output DVDD = 4.75 to 5.25V DVDD - 4.75 to 5.25V TEST CONDITIONS MIN 50 -2.0 -0.5 1.8 9.0 -5 2.15 1.8 6 3 40 50 TYP 10 1.92 9.6 40 1.92 14 50 42 55 MAX 2.0 0.5 2.0 10 1 50 5 0.85 2.0 UNITS Bit MHz LSB LSB V mA mV mA A A V V V ns ns ns pV/s dB dB
Precision Guaranteed Output Voltage Range Setup Time Hold Time Propagation Delay Time Glitch Energy Cross Talk SNR NOTE:
Full scale voltage for each channel 2. Output full scale ratio = ------------------------------------------------------------------------------------------------------------------------ - 1 x 100% . Average of full scale voltage for each channel
10-4
HI2309 Test Circuits
10 10-BIT COUNTER WITH LATCH 10 10 RO TO R9 1 TO 10 G0 TO G9 11 TO 20 B0 TO B9 21 TO 30 35 VB RO 42 200 AVSS 43 GO 44 AVSS 45 BO 46 CLK 50MHz SQUARE WAVE DVSS 31 RCK 32 GCK 33 BCK AVSS 47 VG 38 VREF 37 2V IREF 36 3.3K HI2309 AVSS 0.1 AVSS OSCILLOSCOPE 200 0.1 AVSS 200 AVSS AVDD
FIGURE 1. MAXIMUM CONVERSION RATE TEST CIRCUIT
10 10-BIT COUNTER WITH LATCH 10 10
RO TO R9 1 TO 10 G0 TO G9 11 TO 20 B0 TO B9 21 TO 30 35 VB
RO 42 200 AVSS 43 GO 44 AVSS 45 BO 46 AVSS OSCILLOSCOPE 200 AVSS 200 AVSS 2V 0.1 3.3K AVDD
DELAY CONTROLLER CLK 50MHz SQUARE WAVE
0.1 DVSS
31 RCK DELAY CONTROLLER 32 GCK 33 BCK
AVSS 47 VG 38 VREF 37 IREF 36 HI2309 AVSS
FIGURE 2. SETUP HOLD TIME GLITCH ENERGY TEST CIRCUIT
10-5
HI2309 Test Circuits
(Continued)
DVDD 10 10 10
RO TO R9 1 TO 10 G0 TO G9 11 TO 20 B0 TO B9 21 TO 30 35 VB
RO 42 200 AVSS 43 GO 44 AVSS 45 BO 46 AVSS 200 SPECTRUM ANALYZER
DIGITAL WAVEFORM GENERATOR
0.1 DVSS CLK 50MHz SQUARE WAVE
AVSS 200
31 RCK 32 GCK 33 BCK
AVSS 47 VG 38 VREF 37 IREF 36 3.3K HI2309 AVSS 2V 0.1
AVSS AVDD
FIGURE 3. CROSS TALK TEST CIRCUIT
10 10-BIT COUNTER WITH LATCH 10 10 RO TO R9 1 TO 10 G0 TO G9 11 TO 20 B0 TO B9 21 TO 30 35 VB RO 42 200 AVSS 43 GO 44 AVSS 45 BO 46 CLK 50MHz SQUARE WAVE DVSS 31 RCK 32 GCK 33 BCK AVSS 47 VG 38 VREF 37 IREF 36 3.3K HI2309 AVSS 2V 0.1 AVSS OSCILLOSCOPE 200 AVSS 200 AVSS AVDD
0.1
FIGURE 4. DC CHARACTERISTICS TEST CIRCUIT
10-6
HI2309 Test Circuits
(Continued)
10 10-BIT COUNTER WITH LATCH 10 10
RO TO R9 1 TO 10 G0 TO G9 11 TO 20 B0 TO B9 21 TO 30 35 VB
RO 42 200 AVSS 43 GO 44 AVSS 45 BO 46 AVSS OSCILLOSCOPE 200
0.1 DELAY CONTROLLER CLK 50MHz SQUARE WAVE DVSS
AVSS 200 AVSS AVDD 0.1 3.3K
31 RCK 32 GCK
AVSS 47 VG 38 VREF 37 2V IREF 36 HI2309 AVSS
DELAY CONTROLLER
33 BCK
FIGURE 5. PROPAGATION DELAY TIME TEST CIRCUIT
ALL "1" DIGITAL WAVEFORM GENERATOR
10 10
RO TO R9 1 TO 10 G0 TO G9 11 TO 20 B0 TO B9 21 TO 30 35 VB
RO 42 200 AVSS 43 GO 44 AVSS 45 BO 46 AVSS 200 AVSS 200 AVSS AVDD 0.1 3.3K SPECTRUM ANALYZER
ALL "1"
10
0.1 DVSS
31 RCK CLK 50MHz SQUARE WAVE 32 GCK 33 BCK
AVSS 47 VG 38 VREF 37 2V IREF 36 HI2309 AVSS
FIGURE 6. SNR TEST CIRCUIT
10-7
HI2309 Application Circuit
C R2 C CLOCK INPUT 36 37 R4 C C C 38 39 40 41 R1 42 43 44 R1 45 46 R1 47 48 1 LSB 2 3 4 5 6 7 8 9 10 11 12 LSB HI2309 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 AVSS DVSS AVDD DVDD G CH INPUT LSB B CH INPUT
R3
R CH INPUT
* When the power supply (AV DD and DV DD is 5.0. * R1 - 200. * R2 = 3.3k. * R3 = 3.0k. * R4 = 2.0k. * C = 0.1F.
Application circuits shown are typical examples illustrating the operation of the devices. Intersil cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Typical Performance Curves
OUTPUT FULL SCALE VOLTAGE (V)
2.0 GLITCH ENERGY (pV/S) 1.0 REFERENCE VOLTAGE (V) 2.0 100
1.0
50
100 OUTPUT RESISTANCE ()
200
FIGURE 7. OUTPUT FULL SCALE VOLTAGE vs REFERENCE VOLTAGE
FIGURE 8. OUTPUT RESISTANCE vs GLITCH ENERGY
10-8
Typical Performance Curves
OUTPUT FULL SCALE VOLTAGE (V)
(Continued)
V = 0.02mV/oC 1.95 CURRENT CONSUMPTION (mA) -25 0 25 50 75 50
1.90
40
0
10
1
5
10
15
20
AMBIENT TEMPERATURE (oC)
OUTPUT FREQUENCY (MHz)
FIGURE 9. OUTPUT FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE
FIGURE 10. OUTPUT FREQUENCY vs CURRENT CONSUMPTION
Standard Measurement Conditions and Description
VDD = 5.0V. VREF = 2.0V. R = 200. 16R = 3.3k. TA = 25oC. VREF in Figure 9 is fixed to 2VDC without resistor dividing. Input data in Figure 10 = all "0" and "1" of rectangular wave, clock frequency = 50MHz for a total value of three channels.
time. Set the best values according to the purpose of use. Correlation Between Data and Clock: For HI2309 to display the desired performance as a D/A converter, the data transmitted from outside and the clock must be synchronized properly. Adjust the setup time (tS) and hold time (tH ) as specified in "Electrical Characteristics." VDD , VSS : Separate the analog and digital signals around the device to reduce noise effects. Bypass the VDD pin to each GND with a 0.1F ceramic capacitor as near as possible to the pin for both digital and analog signals. Latch Up: The AVDD and DV DD pins must be able to share the same power supply of the board. This is to prevent latch up caused by potential difference between the two pins when the power is turned on. IREF Pin: The IREF pin is very sensitive to improve the AC Characteristics. Pay attention for capacitance component not to attach to this pin because its output may become unstable. VG Pin: It is recommended to use a 1F capacitor to improve the AC Characteristics, though the typical capacitance value externally connected to the VG Pin is 0.1F.
Notes On Operation
Selecting the Output Resistance: HI2309 is a current output type D/A converter. To create the output voltage, connect the resistor to the current output pin. Specifications: Output full scale voltage VFS Max = 2.0 [V]. Output full scale current IFS Max = 10 [mA]. Calculate the output resistance from VFS = IFS x R. Connect a resistance sixteen times the output resistance to the reference current pin IREF . In some cases, this value may not exist, a similar value can be used instead. Note that the VFS will be the following: VFS = V REF x 16 R/R'. R is the resistor to be connected to the IO and R' is the resistor to be connected to the IREF . Power consumption can be reduced by increasing the resistance, but this will on the contrary, increase the glitch energy and data setting
10-9

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